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| DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a LOW-to-HIGH level transition of the clock input, if the enable input is LOW. A HIGH at the enable input inhibits counting. Level changes at either the enable input or the down/up input should be made only when the clock input is HIGH. The direction of the count is determined by the level of the down/up input. When LOW, the counter counts up and when HIGH, it counts down. The counter is fully programmable; that is, the outputs may be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. Features s Counts binary s Single down/up count control line s Count enable control input s Ripple clock output for cascading s Asynchronously presettable with load control s Parallel outputs s Cascadable for n-bit applications s Average propagation delay 20 ns s Typical clock frequency 25 MHz s Typical power dissipation 100 mW Ordering Code: Order Number DM74LS191M DM74LS191N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 1999 Fairchild Semiconductor Corporation DS006405.prf www.fairchildsemi.com DM74LS191 Connection Diagram Timing Diagram www.fairchildsemi.com 2 DM74LS191 Logic Diagram Pin (16) = VCC, Pin (8) = GND 3 www.fairchildsemi.com DM74LS191 Absolute Maximum Ratings(Note 1) Storage Temperature Range Input Voltage Operating Free Air Temp. Range Supply Voltage -65C to +150C 7V 0C to +70C 7V Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tW tSU tH tEN TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Pulse Width (Note 2) Data Setup Time (Note 2) Data Hold Time (Note 2) Enable Time to Clock (Note 2) Free Air Operating Temperature Clock Load 0 25 35 20 0 30 0 70 ns ns ns C Parameter Min 4.75 2 0.8 -0.4 8 20 Nom 5 Max 5.25 Units V V V mA mA MHz ns Note 2: TA = 25C and VCC = 5V. DC Electrical Characteristics Symbol VI VOH VOL Parameter Input Clamp Voltage Conditions VCC = Min, II = - 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min II IIH IIL IOS ICC Input Current @ Max Input Voltage VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 4) VCC = Max (Note 5) Enable Others Enable Others Enable Others Mil Com -20 -20 20 Mil Com 2.5 2.7 3.4 3.4 0.25 0.35 0.25 0.4 0.5 0.4 0.3 0.1 60 20 -1.08 -0.4 -100 -100 35 mA mA mA A mA V V Min Typ (Note 3) -1.5 V Max Units HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Note 3: All typicals are at VCC = 5V, TA = 25C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all inputs grounded and all outputs open. www.fairchildsemi.com 4 DM74LS191 AC Electrical Characteristics From (Input) Symbol Parameter To (Output) 20 Load to Any Q Load to Any Q Data to Any Q Data to Any Q Clock to Ripple Clock Clock to Ripple Clock Clock to Any Q Clock to Any Q Clock to Max/Min Clock to Max/Min Up/Down to Ripple Clock Up/Down to Ripple Clock Down/Up to Max/Min Down/Up to Max/Min Enable to Ripple Clock Enable to Ripple Clock 33 42 ns 33 36 ns 33 42 ns 33 36 ns 45 54 ns 45 50 ns 52 65 ns 42 47 ns 36 45 ns 24 29 ns 24 33 ns 20 24 ns 50 62 ns 22 26 ns 50 59 ns 33 CL = 15 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output 43 ns Max 20 RL = 2 k CL = 50 pF Min Max MHz Units 5 www.fairchildsemi.com DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS012, 0.150" Narrow Body Package Number M16A 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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